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Introduction to computer organization. Computer instruction set. Machine language. Data processing. Arithmetic unit: Carry look-ahead adders, subtractors, and shifters. Logic unit. Combinational and sequential multipliers and dividers. Floating-point number representation and arithmetic. Data path design. Control unit design. Microprogramming. Pipelining. Discussion, one hour weekly.
Third Year
Electronic devices. Diodes and transistors. BJT gates. RTL basic gates. RTL buffer. DTL basic gate. TTL Structure: operation, I/O characteristics, power dissipation, low power TTL, High-speed TTL, open-collector TTL, and Shottkey TTL. Main features of basic ECL gates. MOS gates. NMOS inverter and gates. CMOS inverter and gates. CMOS tri-state gates. Bilateral switches. Comparison and interfacing of logic families. Semiconductor ROM and RAM. A/D and D/A conversion. Timing circuits. Monostable and astable multivibrators. IC multivibrators. Discussion, one hour weekly.
Fourth Year
Review of Digital Logic fundamentals. Combinational circuits: Representations (tables, maps, cubes, trees, diagrams), Analysis, Synthesis, and Optimization (MISO Minimization: Quine-McClusky, Espresso, SIS, and MIMO Minimization). Complex Registers, complex Counters, and Memory Units: SRAM and DRAM. Hardware Description Languages: VHDL and Verilog. FSM Minimization techniques: Graphical, Mealy FSM, Row Matching, and Implication Chart. Abstract (Algorithmic) State Machine (ASM) fundamentals. FSM partitioning methods. Asynchronous DSD techniques. Programmable logic devices (PLDs) and CPLDs. RAM and ROM systems and timing diagrams. PALs, GALs, and PLAs. Field Programmable Gate Arrays (FPGAs): Xilinx and Alterra FPGAs. Review of Computer Design fundamentals. Review of Microcontrollers and Embedded Systems fundamentals. Full FSM-based design and hardwired versus programmable implementations of a computerized digital system for: Control Unit, Data Path, Memory hierarchy, and Software and Hardware Interfacing. DSD using Systolic Architectures. Systems on chip (SOC). UC Berkeley CAD and optimization tools. Power considerations in DSD. Timing considerations in DSD. Testing and verification of digital systems. New DSD in emerging technologies.
Fifth Year